Line data    Source code

       1             : /*
       2             :  * Copyright (c) 2016 Cisco and/or its affiliates.
       3             :  * Licensed under the Apache License, Version 2.0 (the "License");
       4             :  * you may not use this file except in compliance with the License.
       5             :  * You may obtain a copy of the License at:
       6             :  *
       7             :  *     http://www.apache.org/licenses/LICENSE-2.0
       8             :  *
       9             :  * Unless required by applicable law or agreed to in writing, software
      10             :  * distributed under the License is distributed on an "AS IS" BASIS,
      11             :  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      12             :  * See the License for the specific language governing permissions and
      13             :  * limitations under the License.
      14             :  */
      15             : /*
      16             :  * pci.c: Linux user space PCI bus management.
      17             :  *
      18             :  * Copyright (c) 2008 Eliot Dresselhaus
      19             :  *
      20             :  * Permission is hereby granted, free of charge, to any person obtaining
      21             :  * a copy of this software and associated documentation files (the
      22             :  * "Software"), to deal in the Software without restriction, including
      23             :  * without limitation the rights to use, copy, modify, merge, publish,
      24             :  * distribute, sublicense, and/or sell copies of the Software, and to
      25             :  * permit persons to whom the Software is furnished to do so, subject to
      26             :  * the following conditions:
      27             :  *
      28             :  * The above copyright notice and this permission notice shall be
      29             :  * included in all copies or substantial portions of the Software.
      30             :  *
      31             :  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
      32             :  *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
      33             :  *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
      34             :  *  NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
      35             :  *  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
      36             :  *  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
      37             :  *  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
      38             :  */
      39             : 
      40             : #include <vlib/vlib.h>
      41             : #include <vlib/pci/pci.h>
      42             : #include <vlib/unix/unix.h>
      43             : 
      44             : #include <sys/types.h>
      45             : #include <sys/stat.h>
      46             : #include <fcntl.h>
      47             : #include <dirent.h>
      48             : #include <sys/ioctl.h>
      49             : #include <net/if.h>
      50             : #include <linux/ethtool.h>
      51             : #include <linux/sockios.h>
      52             : 
      53             : vlib_pci_main_t pci_main;
      54             : 
      55         575 : VLIB_REGISTER_LOG_CLASS (pci_log, static) = {
      56             :   .class_name = "pci",
      57             : };
      58             : 
      59             : #define log_debug(h, f, ...)                                                  \
      60             :   vlib_log (VLIB_LOG_LEVEL_DEBUG, pci_log.class, "%U: " f,                    \
      61             :             format_vlib_pci_log, h, ##__VA_ARGS__)
      62             : 
      63             : u8 *
      64           0 : format_vlib_pci_log (u8 *s, va_list *va)
      65             : {
      66           0 :   vlib_pci_dev_handle_t h = va_arg (*va, vlib_pci_dev_handle_t);
      67           0 :   return format (s, "%U", format_vlib_pci_addr,
      68             :                  vlib_pci_get_addr (vlib_get_main (), h));
      69             : }
      70             : 
      71             : vlib_pci_device_info_t *__attribute__ ((weak))
      72           0 : vlib_pci_get_device_info (vlib_main_t *vm, vlib_pci_addr_t *addr,
      73             :                           clib_error_t **error)
      74             : {
      75           0 :   if (error)
      76           0 :     *error = clib_error_return (0, "unsupported");
      77           0 :   return 0;
      78             : }
      79             : 
      80             : clib_error_t *__attribute__ ((weak))
      81           0 : vlib_pci_get_device_root_bus (vlib_pci_addr_t *addr, vlib_pci_addr_t *root_bus)
      82             : {
      83           0 :   return 0;
      84             : }
      85             : 
      86           0 : vlib_pci_addr_t * __attribute__ ((weak)) vlib_pci_get_all_dev_addrs ()
      87             : {
      88           0 :   return 0;
      89             : }
      90             : 
      91             : static clib_error_t *
      92           0 : _vlib_pci_config_set_control_bit (vlib_main_t *vm, vlib_pci_dev_handle_t h,
      93             :                                   u16 bit, int new_val, int *already_set)
      94             : {
      95             :   u16 control, old;
      96             :   clib_error_t *err;
      97             : 
      98           0 :   err = vlib_pci_read_write_config (
      99             :     vm, h, VLIB_READ, STRUCT_OFFSET_OF (vlib_pci_config_t, command), &old,
     100             :     STRUCT_SIZE_OF (vlib_pci_config_t, command));
     101             : 
     102           0 :   if (err)
     103           0 :     return err;
     104             : 
     105           0 :   control = new_val ? old | bit : old & ~bit;
     106           0 :   *already_set = old == control;
     107           0 :   if (*already_set)
     108           0 :     return 0;
     109             : 
     110           0 :   return vlib_pci_read_write_config (
     111             :     vm, h, VLIB_WRITE, STRUCT_OFFSET_OF (vlib_pci_config_t, command), &control,
     112             :     STRUCT_SIZE_OF (vlib_pci_config_t, command));
     113             : }
     114             : 
     115             : clib_error_t *
     116           0 : vlib_pci_intr_enable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
     117             : {
     118           0 :   const vlib_pci_config_reg_command_t cmd = { .intx_disable = 1 };
     119             :   clib_error_t *err;
     120             :   int already_set;
     121             : 
     122           0 :   err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 0, &already_set);
     123           0 :   log_debug (h, "interrupt%senabled", already_set ? " " : " already ");
     124           0 :   return err;
     125             : }
     126             : 
     127             : clib_error_t *
     128           0 : vlib_pci_intr_disable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
     129             : {
     130           0 :   const vlib_pci_config_reg_command_t cmd = { .intx_disable = 1 };
     131             :   clib_error_t *err;
     132             :   int already_set;
     133             : 
     134           0 :   err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 1, &already_set);
     135           0 :   log_debug (h, "interrupt%sdisabled", already_set ? " " : " already ");
     136           0 :   return err;
     137             : }
     138             : 
     139             : clib_error_t *
     140           0 : vlib_pci_bus_master_enable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
     141             : {
     142           0 :   const vlib_pci_config_reg_command_t cmd = { .bus_master = 1 };
     143             :   clib_error_t *err;
     144             :   int already_set;
     145             : 
     146           0 :   err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 1, &already_set);
     147           0 :   log_debug (h, "bus-master%senabled", already_set ? " " : " already ");
     148           0 :   return err;
     149             : }
     150             : 
     151             : clib_error_t *
     152           0 : vlib_pci_bus_master_disable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
     153             : {
     154           0 :   const vlib_pci_config_reg_command_t cmd = { .bus_master = 1 };
     155             :   clib_error_t *err;
     156             :   int already_set;
     157             : 
     158           0 :   err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 0, &already_set);
     159           0 :   log_debug (h, "bus-master%sdisabled", already_set ? " " : " already ");
     160           0 :   return err;
     161             : }
     162             : 
     163             : clib_error_t *
     164           0 : vlib_pci_function_level_reset (vlib_main_t *vm, vlib_pci_dev_handle_t h)
     165             : {
     166             :   vlib_pci_config_t cfg;
     167             :   pci_capability_pcie_t *cap;
     168             :   pci_capability_pcie_dev_control_t dev_control;
     169             :   clib_error_t *err;
     170             :   u8 offset;
     171             : 
     172           0 :   log_debug (h, "function level reset");
     173             : 
     174           0 :   err = vlib_pci_read_write_config (vm, h, VLIB_READ, 0, &cfg, sizeof (cfg));
     175           0 :   if (err)
     176           0 :     return err;
     177             : 
     178           0 :   offset = cfg.cap_ptr;
     179             :   do
     180             :     {
     181           0 :       cap = (pci_capability_pcie_t *) (cfg.data + offset);
     182             : 
     183           0 :       if (cap->capability_id == PCI_CAP_ID_PCIE)
     184           0 :         break;
     185             : 
     186           0 :       offset = cap->next_offset;
     187             :     }
     188           0 :   while (offset);
     189             : 
     190           0 :   if (cap->capability_id != PCI_CAP_ID_PCIE)
     191           0 :     return clib_error_return (0, "PCIe capability config not found");
     192             : 
     193           0 :   if (cap->dev_caps.flr_capable == 0)
     194           0 :     return clib_error_return (0, "PCIe function level reset not supported");
     195             : 
     196           0 :   dev_control = cap->dev_control;
     197           0 :   dev_control.function_level_reset = 1;
     198             : 
     199           0 :   if ((err = vlib_pci_write_config_u16 (
     200             :          vm, h, offset + STRUCT_OFFSET_OF (pci_capability_pcie_t, dev_control),
     201             :          &dev_control.as_u16)))
     202           0 :     return err;
     203             : 
     204           0 :   return 0;
     205             : }
     206             : 
     207             : static clib_error_t *
     208           0 : show_pci_fn (vlib_main_t * vm,
     209             :              unformat_input_t * input, vlib_cli_command_t * cmd)
     210             : {
     211           0 :   vlib_pci_addr_t *addr = 0, *addrs;
     212           0 :   int show_all = 0;
     213           0 :   u8 *s = 0;
     214             : 
     215           0 :   while (unformat_check_input (input) != UNFORMAT_END_OF_INPUT)
     216             :     {
     217           0 :       if (unformat (input, "all"))
     218           0 :         show_all = 1;
     219             :       else
     220           0 :         return clib_error_return (0, "unknown input `%U'",
     221             :                                   format_unformat_error, input);
     222             :     }
     223             : 
     224           0 :   vlib_cli_output (vm, "%-13s%-5s%-12s%-14s%-16s%-32s%s",
     225             :                    "Address", "Sock", "VID:PID", "Link Speed", "Driver",
     226             :                    "Product Name", "Vital Product Data");
     227             : 
     228           0 :   addrs = vlib_pci_get_all_dev_addrs ();
     229             : 
     230           0 :   vec_foreach (addr, addrs)
     231             :     {
     232             :       vlib_pci_device_info_t *d;
     233           0 :       d = vlib_pci_get_device_info (vm, addr, 0);
     234             : 
     235           0 :       if (!d)
     236           0 :         continue;
     237             : 
     238           0 :       if (d->device_class != PCI_CLASS_NETWORK_ETHERNET && !show_all)
     239           0 :         continue;
     240             : 
     241           0 :       vec_reset_length (s);
     242           0 :       if (d->numa_node >= 0)
     243           0 :         s = format (s, "  %d", d->numa_node);
     244             : 
     245           0 :       vlib_cli_output (
     246             :         vm, "%-13U%-5v%04x:%04x   %-14U%-16s%-32v%U", format_vlib_pci_addr,
     247           0 :         addr, s, d->vendor_id, d->device_id, format_vlib_pci_link_speed, d,
     248           0 :         d->driver_name ? (char *) d->driver_name : "", d->product_name,
     249             :         format_vlib_pci_vpd, d->vpd_r, (u8 *) 0);
     250           0 :       vlib_pci_free_device_info (d);
     251             :     }
     252             : 
     253           0 :   vec_free (s);
     254           0 :   vec_free (addrs);
     255           0 :   return 0;
     256             : }
     257             : 
     258             : uword
     259           0 : unformat_vlib_pci_addr (unformat_input_t * input, va_list * args)
     260             : {
     261           0 :   vlib_pci_addr_t *addr = va_arg (*args, vlib_pci_addr_t *);
     262             :   u32 x[4];
     263             : 
     264           0 :   if (!unformat (input, "%x:%x:%x.%x", &x[0], &x[1], &x[2], &x[3]))
     265           0 :     return 0;
     266             : 
     267           0 :   addr->domain = x[0];
     268           0 :   addr->bus = x[1];
     269           0 :   addr->slot = x[2];
     270           0 :   addr->function = x[3];
     271             : 
     272           0 :   return 1;
     273             : }
     274             : 
     275             : u8 *
     276      170775 : format_vlib_pci_addr (u8 * s, va_list * va)
     277             : {
     278      170775 :   vlib_pci_addr_t *addr = va_arg (*va, vlib_pci_addr_t *);
     279      341550 :   return format (s, "%04x:%02x:%02x.%x", addr->domain, addr->bus,
     280      170775 :                  addr->slot, addr->function);
     281             : }
     282             : 
     283             : u8 *
     284           0 : format_vlib_pci_link_port (u8 *s, va_list *va)
     285             : {
     286           0 :   vlib_pci_config_t *c = va_arg (*va, vlib_pci_config_t *);
     287           0 :   pci_capability_pcie_t *r = pci_config_find_capability (c, PCI_CAP_ID_PCIE);
     288             : 
     289           0 :   if (!r)
     290           0 :     return format (s, "unknown");
     291             : 
     292           0 :   return format (s, "P%d", r->link_caps.port_number);
     293             : }
     294             : 
     295             : static u8 *
     296           0 : _vlib_pci_link_speed (u8 *s, u8 speed, u8 width)
     297             : {
     298             :   static char *speeds[] = {
     299             :     [1] = "2.5", [2] = "5.0", [3] = "8.0", [4] = "16.0", [5] = "32.0"
     300             :   };
     301             : 
     302           0 :   if (speed >= ARRAY_LEN (speeds) || speeds[speed] == 0)
     303           0 :     s = format (s, "unknown speed");
     304             :   else
     305           0 :     s = format (s, "%s GT/s", speeds[speed]);
     306             : 
     307           0 :   return format (s, " x%u", width);
     308             : }
     309             : 
     310             : u8 *
     311           0 : format_vlib_pci_link_speed (u8 *s, va_list *va)
     312             : {
     313           0 :   vlib_pci_config_t *c = va_arg (*va, vlib_pci_config_t *);
     314           0 :   pci_capability_pcie_t *r = pci_config_find_capability (c, PCI_CAP_ID_PCIE);
     315             : 
     316           0 :   if (!r)
     317           0 :     return format (s, "unknown");
     318             : 
     319           0 :   return _vlib_pci_link_speed (s, r->link_status.link_speed,
     320           0 :                                r->link_status.negotiated_link_width);
     321             : }
     322             : 
     323             : u8 *
     324           0 : format_vlib_pci_link_speed_cap (u8 *s, va_list *va)
     325             : {
     326           0 :   vlib_pci_config_t *c = va_arg (*va, vlib_pci_config_t *);
     327           0 :   pci_capability_pcie_t *r = pci_config_find_capability (c, PCI_CAP_ID_PCIE);
     328             : 
     329           0 :   if (!r)
     330           0 :     return format (s, "unknown");
     331             : 
     332           0 :   return _vlib_pci_link_speed (s, r->link_caps.max_link_speed,
     333           0 :                                r->link_caps.max_link_width);
     334             : }
     335             : 
     336             : u8 *
     337           0 : format_vlib_pci_vpd (u8 * s, va_list * args)
     338             : {
     339           0 :   u8 *data = va_arg (*args, u8 *);
     340           0 :   u8 *id = va_arg (*args, u8 *);
     341           0 :   u32 indent = format_get_indent (s);
     342           0 :   char *string_types[] = { "PN", "EC", "SN", "MN", 0 };
     343           0 :   uword p = 0;
     344           0 :   int first_line = 1;
     345             : 
     346           0 :   if (vec_len (data) < 3)
     347           0 :     return s;
     348             : 
     349           0 :   while (p + 3 < vec_len (data))
     350             :     {
     351             : 
     352           0 :       if (data[p] == 0 && data[p + 1] == 0)
     353           0 :         return s;
     354             : 
     355           0 :       if (p + data[p + 2] > vec_len (data))
     356           0 :         return s;
     357             : 
     358           0 :       if (id == 0)
     359             :         {
     360           0 :           int is_string = 0;
     361           0 :           char **c = string_types;
     362             : 
     363           0 :           while (c[0])
     364             :             {
     365           0 :               if (*(u16 *) & data[p] == *(u16 *) c[0])
     366           0 :                 is_string = 1;
     367           0 :               c++;
     368             :             }
     369             : 
     370           0 :           if (data[p + 2])
     371             :             {
     372           0 :               if (!first_line)
     373           0 :                 s = format (s, "\n%U", format_white_space, indent);
     374             :               else
     375             :                 {
     376           0 :                   first_line = 0;
     377           0 :                   s = format (s, " ");
     378             :                 }
     379             : 
     380           0 :               s = format (s, "%c%c: ", data[p], data[p + 1]);
     381           0 :               if (is_string)
     382           0 :                 vec_add (s, data + p + 3, data[p + 2]);
     383             :               else
     384             :                 {
     385             :                   int i;
     386           0 :                   const int max_bytes = 8;
     387           0 :                   s = format (s, "0x");
     388           0 :                   for (i = 0; i < clib_min (data[p + 2], max_bytes); i++)
     389           0 :                     s = format (s, " %02x", data[p + 3 + i]);
     390             : 
     391           0 :                   if (data[p + 2] > max_bytes)
     392           0 :                     s = format (s, " ...");
     393             :                 }
     394             :             }
     395             :         }
     396           0 :       else if (*(u16 *) & data[p] == *(u16 *) id)
     397             :         {
     398           0 :           vec_add (s, data + p + 3, data[p + 2]);
     399           0 :           return s;
     400             :         }
     401             : 
     402           0 :       p += 3 + data[p + 2];
     403             :     }
     404             : 
     405           0 :   return s;
     406             : }
     407             : 
     408      285289 : VLIB_CLI_COMMAND (show_pci_command, static) = {
     409             :   .path = "show pci",
     410             :   .short_help = "show pci [all]",
     411             :   .function = show_pci_fn,
     412             : };