Line data Source code
1 : /* SPDX-License-Identifier: Apache-2.0 2 : * Copyright(c) 2022 Cisco Systems, Inc. 3 : */ 4 : 5 : #ifdef __x86_64__ 6 : 7 : #include <vppinfra/format.h> 8 : #include <vppinfra/error.h> 9 : #include <vppinfra/perfmon/perfmon.h> 10 : 11 : static u8 * 12 0 : format_perfmon_bundle_core_power (u8 *s, va_list *args) 13 : { 14 0 : clib_perfmon_ctx_t __clib_unused *ctx = va_arg (*args, clib_perfmon_ctx_t *); 15 0 : clib_perfmon_capture_t *c = va_arg (*args, clib_perfmon_capture_t *); 16 0 : u32 col = va_arg (*args, int); 17 0 : u64 *d = c->data; 18 : 19 0 : switch (col) 20 : { 21 0 : case 0: 22 0 : return format (s, "%7.1f %%", (f64) 100 * d[1] / d[0]); 23 0 : case 1: 24 0 : return format (s, "%7.1f %%", (f64) 100 * d[2] / d[0]); 25 0 : case 2: 26 0 : return format (s, "%7.1f %%", (f64) 100 * d[3] / d[0]); 27 0 : default: 28 0 : return s; 29 : } 30 : } 31 : 32 : #define PERF_INTEL_CODE(event, umask) ((event) | (umask) << 8) 33 : 34 642 : CLIB_PERFMON_BUNDLE (core_power) = { 35 : .name = "core-power", 36 : .desc = 37 : "Core cycles where the core was running under specific turbo schedule.", 38 : .type = PERF_TYPE_RAW, 39 : .config[0] = PERF_INTEL_CODE (0x3c, 0x00), 40 : .config[1] = PERF_INTEL_CODE (0x28, 0x07), 41 : .config[2] = PERF_INTEL_CODE (0x28, 0x18), 42 : .config[3] = PERF_INTEL_CODE (0x28, 0x20), 43 : .n_events = 4, 44 : .format_fn = format_perfmon_bundle_core_power, 45 : .column_headers = CLIB_STRING_ARRAY ("Level 0", "Level 1", "Level 2"), 46 : }; 47 : 48 : #endif