Line data    Source code

       1             : /*
       2             :  * Copyright (c) 2022 Intel and/or its affiliates.
       3             :  * Licensed under the Apache License, Version 2.0 (the "License");
       4             :  * you may not use this file except in compliance with the License.
       5             :  * You may obtain a copy of the License at:
       6             :  *
       7             :  *     http://www.apache.org/licenses/LICENSE-2.0
       8             :  *
       9             :  * Unless required by applicable law or agreed to in writing, software
      10             :  * distributed under the License is distributed on an "AS IS" BASIS,
      11             :  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      12             :  * See the License for the specific language governing permissions and
      13             :  * limitations under the License.
      14             :  */
      15             : 
      16             : #include <perfmon/perfmon.h>
      17             : #include <perfmon/intel/core.h>
      18             : 
      19             : enum
      20             : {
      21             :   PORT0 = 0,
      22             :   PORT1 = 1,
      23             :   PORT5 = 2,
      24             :   PORT6 = 3,
      25             :   PORT2_3 = 4,
      26             :   PORT4_9 = 5,
      27             :   PORT7_8 = 6,
      28             :   DISTRIBUTED = 7,
      29             : };
      30             : 
      31             : static u8 *
      32           0 : format_intel_backend_bound_core (u8 *s, va_list *args)
      33             : {
      34           0 :   perfmon_node_stats_t *ss = va_arg (*args, perfmon_node_stats_t *);
      35           0 :   int row = va_arg (*args, int);
      36           0 :   f64 sv = 0;
      37             : 
      38           0 :   if (!ss->n_packets)
      39           0 :     return s;
      40             : 
      41           0 :   if (0 == row)
      42             :     {
      43           0 :       sv = ss->value[DISTRIBUTED] / ss->n_packets;
      44             : 
      45           0 :       s = format (s, "%.0f", sv);
      46           0 :       return s;
      47             :     }
      48             : 
      49           0 :   switch (row)
      50             :     {
      51           0 :     case 1:
      52           0 :       sv = ss->value[PORT0] / (f64) ss->value[DISTRIBUTED];
      53           0 :       break;
      54           0 :     case 2:
      55           0 :       sv = ss->value[PORT1] / (f64) ss->value[DISTRIBUTED];
      56           0 :       break;
      57           0 :     case 3:
      58           0 :       sv = ss->value[PORT5] / (f64) ss->value[DISTRIBUTED];
      59           0 :       break;
      60           0 :     case 4:
      61           0 :       sv = ss->value[PORT6] / (f64) ss->value[DISTRIBUTED];
      62           0 :       break;
      63           0 :     case 5:
      64           0 :       sv = (ss->value[PORT2_3]) / (f64) (2 * ss->value[DISTRIBUTED]);
      65           0 :       break;
      66           0 :     case 6:
      67           0 :       sv = (ss->value[PORT4_9] + ss->value[PORT7_8]) /
      68           0 :            (f64) (4 * ss->value[DISTRIBUTED]);
      69           0 :       break;
      70             :     }
      71             : 
      72           0 :   sv = clib_max (sv * 100, 0);
      73           0 :   s = format (s, "%04.1f", sv);
      74             : 
      75           0 :   return s;
      76             : }
      77             : 
      78             : static perfmon_cpu_supports_t backend_bound_core_cpu_supports[] = {
      79             :   { clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE },
      80             : };
      81             : 
      82         559 : PERFMON_REGISTER_BUNDLE (intel_core_backend_bound_core) = {
      83             :   .name = "td-backend-core",
      84             :   .description = "Topdown BackEnd-bound Core - % cycles core resources busy",
      85             :   .source = "intel-core",
      86             :   .events[0] = INTEL_CORE_E_UOPS_DISPATCHED_PORT_0,       /* 0xFF */
      87             :   .events[1] = INTEL_CORE_E_UOPS_DISPATCHED_PORT_1,       /* 0xFF */
      88             :   .events[2] = INTEL_CORE_E_UOPS_DISPATCHED_PORT_5,       /* 0xFF */
      89             :   .events[3] = INTEL_CORE_E_UOPS_DISPATCHED_PORT_6,       /* 0xFF */
      90             :   .events[4] = INTEL_CORE_E_UOPS_DISPATCHED_PORT_2_3,     /* 0xFF */
      91             :   .events[5] = INTEL_CORE_E_UOPS_DISPATCHED_PORT_4_9,     /* 0xFF */
      92             :   .events[6] = INTEL_CORE_E_UOPS_DISPATCHED_PORT_7_8,     /* 0xFF */
      93             :   .events[7] = INTEL_CORE_E_CPU_CLK_UNHALTED_DISTRIBUTED, /* 0xFF */
      94             :   .n_events = 8,
      95             :   .format_fn = format_intel_backend_bound_core,
      96             :   .cpu_supports = backend_bound_core_cpu_supports,
      97             :   .n_cpu_supports = ARRAY_LEN (backend_bound_core_cpu_supports),
      98             :   .column_headers = PERFMON_STRINGS ("Clocks/Packet", "%Port0", "%Port1",
      99             :                                      "%Port5", "%Port6", "%Load", "%Store"),
     100             : };