Line data    Source code

       1             : /*
       2             :  * Copyright (c) 2022 Intel and/or its affiliates.
       3             :  * Licensed under the Apache License, Version 2.0 (the "License");
       4             :  * you may not use this file except in compliance with the License.
       5             :  * You may obtain a copy of the License at:
       6             :  *
       7             :  *     http://www.apache.org/licenses/LICENSE-2.0
       8             :  *
       9             :  * Unless required by applicable law or agreed to in writing, software
      10             :  * distributed under the License is distributed on an "AS IS" BASIS,
      11             :  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      12             :  * See the License for the specific language governing permissions and
      13             :  * limitations under the License.
      14             :  */
      15             : 
      16             : #include <perfmon/perfmon.h>
      17             : #include <perfmon/intel/core.h>
      18             : 
      19             : enum
      20             : {
      21             :   DSB_UOPS,
      22             :   MS_UOPS,
      23             :   MITE_UOPS,
      24             :   LSD_UOPS,
      25             : };
      26             : 
      27             : static u8 *
      28           0 : format_intel_frontend_bound_bw_src (u8 *s, va_list *args)
      29             : {
      30           0 :   perfmon_node_stats_t *ss = va_arg (*args, perfmon_node_stats_t *);
      31           0 :   int row = va_arg (*args, int);
      32           0 :   f64 sv = 0;
      33           0 :   f64 uops = ss->value[DSB_UOPS] + ss->value[MS_UOPS] + ss->value[MITE_UOPS] +
      34           0 :              ss->value[LSD_UOPS];
      35             : 
      36           0 :   if (!ss->n_packets)
      37           0 :     return s;
      38             : 
      39           0 :   if (row == 0)
      40             :     {
      41           0 :       sv = uops / ss->n_packets;
      42           0 :       s = format (s, "%.0f", sv);
      43             : 
      44           0 :       return s;
      45             :     }
      46             : 
      47           0 :   switch (row)
      48             :     {
      49           0 :     case 1:
      50           0 :       sv = (ss->value[DSB_UOPS] / uops) * 100;
      51           0 :       break;
      52           0 :     case 2:
      53           0 :       sv = (ss->value[MS_UOPS] / uops) * 100;
      54           0 :       break;
      55           0 :     case 3:
      56           0 :       sv = (ss->value[MITE_UOPS] / uops) * 100;
      57           0 :       break;
      58           0 :     case 4:
      59           0 :       sv = (ss->value[LSD_UOPS] / uops) * 100;
      60           0 :       break;
      61             :     }
      62             : 
      63           0 :   s = format (s, "%04.1f", sv);
      64             : 
      65           0 :   return s;
      66             : }
      67             : 
      68             : static perfmon_cpu_supports_t frontend_bound_bw_cpu_supports_src[] = {
      69             :   { clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE },
      70             : };
      71             : 
      72         559 : PERFMON_REGISTER_BUNDLE (intel_core_frontend_bound_bw_src) = {
      73             :   .name = "td-frontend-bw-src",
      74             :   .description =
      75             :     "Topdown FrontEnd-bound BandWidth - % uops from each uop fetch source",
      76             :   .source = "intel-core",
      77             :   .events[0] = INTEL_CORE_E_IDQ_DSB_UOPS,  /* 0x0F */
      78             :   .events[1] = INTEL_CORE_E_IDQ_MS_UOPS,   /* 0x0F */
      79             :   .events[2] = INTEL_CORE_E_IDQ_MITE_UOPS, /* 0x0F */
      80             :   .events[3] = INTEL_CORE_E_LSD_UOPS,      /* 0x0F */
      81             :   .n_events = 4,
      82             :   .format_fn = format_intel_frontend_bound_bw_src,
      83             :   .cpu_supports = frontend_bound_bw_cpu_supports_src,
      84             :   .n_cpu_supports = ARRAY_LEN (frontend_bound_bw_cpu_supports_src),
      85             :   .column_headers = PERFMON_STRINGS ("UOPs/PKT", "% DSB UOPS", "% MS UOPS",
      86             :                                      "% MITE UOPS", "% LSD UOPS"),
      87             :   .footer =
      88             :     "For more information, see the Intel(R) 64 and IA-32 Architectures\n"
      89             :     "Optimization Reference Manual section on the Front End.",
      90             : };