Line data    Source code

       1             : /*
       2             :  * Copyright (c) 2022 Intel and/or its affiliates.
       3             :  * Licensed under the Apache License, Version 2.0 (the "License");
       4             :  * you may not use this file except in compliance with the License.
       5             :  * You may obtain a copy of the License at:
       6             :  *
       7             :  *     http://www.apache.org/licenses/LICENSE-2.0
       8             :  *
       9             :  * Unless required by applicable law or agreed to in writing, software
      10             :  * distributed under the License is distributed on an "AS IS" BASIS,
      11             :  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      12             :  * See the License for the specific language governing permissions and
      13             :  * limitations under the License.
      14             :  */
      15             : 
      16             : #include <perfmon/perfmon.h>
      17             : #include <perfmon/intel/core.h>
      18             : 
      19             : enum
      20             : {
      21             :   THREAD_P,
      22             :   THREE_UOP,
      23             :   TWO_UOP,
      24             :   ONE_UOP,
      25             :   NO_UOP,
      26             :   FOUR_UOP,
      27             : };
      28             : 
      29             : static u8 *
      30           0 : format_intel_frontend_bound_bw_uops (u8 *s, va_list *args)
      31             : {
      32           0 :   perfmon_node_stats_t *ss = va_arg (*args, perfmon_node_stats_t *);
      33           0 :   int row = va_arg (*args, int);
      34           0 :   f64 sv = 0;
      35           0 :   f64 cycles = ss->value[THREAD_P];
      36             : 
      37           0 :   switch (row)
      38             :     {
      39           0 :     case 0:
      40           0 :       sv = (ss->value[FOUR_UOP] / cycles) * 100;
      41           0 :       break;
      42           0 :     case 1:
      43           0 :       sv = ((ss->value[THREE_UOP] - ss->value[TWO_UOP]) / cycles) * 100;
      44           0 :       break;
      45           0 :     case 2:
      46           0 :       sv = ((ss->value[TWO_UOP] - ss->value[ONE_UOP]) / cycles) * 100;
      47           0 :       break;
      48           0 :     case 3:
      49           0 :       sv = ((ss->value[ONE_UOP] - ss->value[NO_UOP]) / cycles) * 100;
      50           0 :       break;
      51           0 :     case 4:
      52           0 :       sv = (ss->value[NO_UOP] / cycles) * 100;
      53           0 :       break;
      54             :     }
      55             : 
      56           0 :   s = format (s, "%04.1f", sv);
      57             : 
      58           0 :   return s;
      59             : }
      60             : 
      61             : static perfmon_cpu_supports_t frontend_bound_bw_cpu_supports_uops[] = {
      62             :   { clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE },
      63             : };
      64             : 
      65         559 : PERFMON_REGISTER_BUNDLE (intel_core_frontend_bound_bw_uops) = {
      66             :   .name = "td-frontend-bw-uops",
      67             :   .description = "Topdown FrontEnd-bound BandWidth - distribution of "
      68             :                  "uops delivered to frontend",
      69             :   .source = "intel-core",
      70             :   .events[0] = INTEL_CORE_E_CPU_CLK_UNHALTED_THREAD_P, /* 0x0F */
      71             :   .events[1] =
      72             :     INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_3_UOP_DELIV_CORE, /* 0xFF */
      73             :   .events[2] =
      74             :     INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_2_UOP_DELIV_CORE, /* 0xFF */
      75             :   .events[3] =
      76             :     INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_1_UOP_DELIV_CORE, /* 0xFF */
      77             :   .events[4] =
      78             :     INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOP_DELIV_CORE,     /* 0xFF */
      79             :   .events[5] = INTEL_CORE_E_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK, /* 0xFF */
      80             :   .n_events = 6,
      81             :   .format_fn = format_intel_frontend_bound_bw_uops,
      82             :   .cpu_supports = frontend_bound_bw_cpu_supports_uops,
      83             :   .n_cpu_supports = ARRAY_LEN (frontend_bound_bw_cpu_supports_uops),
      84             :   .column_headers = PERFMON_STRINGS ("% 4 UOPS", "% 3 UOPS", "% 2 UOPS",
      85             :                                      "% 1 UOPS", "% 0 UOPS"),
      86             :   .footer =
      87             :     "For more information, see the Intel(R) 64 and IA-32 Architectures\n"
      88             :     "Optimization Reference Manual section on the Front End.",
      89             : };