Line data    Source code

       1             : /*
       2             :  * Copyright (c) 2022 Intel and/or its affiliates.
       3             :  * Licensed under the Apache License, Version 2.0 (the "License");
       4             :  * you may not use this file except in compliance with the License.
       5             :  * You may obtain a copy of the License at:
       6             :  *
       7             :  *     http://www.apache.org/licenses/LICENSE-2.0
       8             :  *
       9             :  * Unless required by applicable law or agreed to in writing, software
      10             :  * distributed under the License is distributed on an "AS IS" BASIS,
      11             :  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      12             :  * See the License for the specific language governing permissions and
      13             :  * limitations under the License.
      14             :  */
      15             : 
      16             : #include <perfmon/perfmon.h>
      17             : #include <perfmon/intel/core.h>
      18             : 
      19             : static const int MS_Switches_Cost = 3;
      20             : static const int BA_Clear_Cost = 10;
      21             : 
      22             : enum
      23             : {
      24             :   ICACHE_MISS,
      25             :   DSB_SWITCHES,
      26             :   RESTEER,
      27             :   MS_SWITCHES,
      28             :   BACLEARS,
      29             :   THREAD,
      30             : };
      31             : 
      32             : static u8 *
      33           0 : format_intel_frontend_bound_lat (u8 *s, va_list *args)
      34             : {
      35           0 :   perfmon_node_stats_t *ss = va_arg (*args, perfmon_node_stats_t *);
      36           0 :   int row = va_arg (*args, int);
      37           0 :   f64 sv = 0;
      38           0 :   f64 cycles = ss->value[THREAD];
      39             : 
      40           0 :   if (!ss->n_packets)
      41           0 :     return s;
      42             : 
      43           0 :   if (!row)
      44             :     {
      45           0 :       sv = ss->value[THREAD] / ss->n_packets;
      46             : 
      47           0 :       s = format (s, "%.0f", sv);
      48             : 
      49           0 :       return s;
      50             :     }
      51             : 
      52           0 :   switch (row)
      53             :     {
      54           0 :     case 1:
      55           0 :       sv = ss->value[ICACHE_MISS] / cycles;
      56           0 :       break;
      57           0 :     case 2:
      58           0 :       sv = ss->value[DSB_SWITCHES] / cycles;
      59           0 :       break;
      60           0 :     case 3:
      61           0 :       sv =
      62           0 :         (ss->value[RESTEER] + (ss->value[BACLEARS] * BA_Clear_Cost)) / cycles;
      63           0 :       break;
      64           0 :     case 4:
      65           0 :       sv = (ss->value[MS_SWITCHES] * MS_Switches_Cost) / cycles;
      66           0 :       break;
      67             :     }
      68             : 
      69           0 :   s = format (s, "%04.1f", sv * 100);
      70             : 
      71           0 :   return s;
      72             : }
      73             : 
      74             : static perfmon_cpu_supports_t frontend_bound_lat_cpu_supports[] = {
      75             :   { clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE },
      76             : };
      77             : 
      78         559 : PERFMON_REGISTER_BUNDLE (intel_core_frontend_bound_lat) = {
      79             :   .name = "td-frontend-lat",
      80             :   .description = "Topdown FrontEnd-bound Latency - % cycles not retiring uops "
      81             :                  "due to frontend latency",
      82             :   .source = "intel-core",
      83             :   .events[0] = INTEL_CORE_E_ICACHE_16B_IFDATA_STALL,          /* 0x0F */
      84             :   .events[1] = INTEL_CORE_E_DSB2MITE_SWITCHES_PENALTY_CYCLES, /* 0x0F */
      85             :   .events[2] = INTEL_CORE_E_INT_MISC_CLEAR_RESTEER_CYCLES,    /* 0xFF */
      86             :   .events[3] = INTEL_CORE_E_IDQ_MS_SWITCHES,                  /* 0x0F */
      87             :   .events[4] = INTEL_CORE_E_BACLEARS_ANY,                     /* 0x0F */
      88             :   .events[5] = INTEL_CORE_E_CPU_CLK_UNHALTED_THREAD_P,        /* FIXED */
      89             :   .n_events = 6,
      90             :   .format_fn = format_intel_frontend_bound_lat,
      91             :   .cpu_supports = frontend_bound_lat_cpu_supports,
      92             :   .n_cpu_supports = ARRAY_LEN (frontend_bound_lat_cpu_supports),
      93             :   .column_headers = PERFMON_STRINGS ("Clocks/Packet", "% iCache Miss",
      94             :                                      "% DSB Switch", "% Branch Resteer",
      95             :                                      "% MS Switch"),
      96             :   .footer =
      97             :     "For more information, see the Intel(R) 64 and IA-32 Architectures\n"
      98             :     "Optimization Reference Manual on the Front End.",
      99             : };