Line data Source code
1 : /*
2 : * Copyright (c) 2021 Intel and/or its affiliates.
3 : * Licensed under the Apache License, Version 2.0 (the "License");
4 : * you may not use this file except in compliance with the License.
5 : * You may obtain a copy of the License at:
6 : *
7 : * http://www.apache.org/licenses/LICENSE-2.0
8 : *
9 : * Unless required by applicable law or agreed to in writing, software
10 : * distributed under the License is distributed on an "AS IS" BASIS,
11 : * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 : * See the License for the specific language governing permissions and
13 : * limitations under the License.
14 : */
15 :
16 : #include <perfmon/perfmon.h>
17 : #include <perfmon/intel/uncore.h>
18 : #include <vlib/pci/pci.h>
19 : #include <vppinfra/format.h>
20 : #include <linux/limits.h>
21 : #include <fcntl.h>
22 : #include <math.h>
23 :
24 : typedef struct
25 : {
26 : u8 socket_id;
27 : u8 sad_id;
28 : u8 iio_unit_id;
29 : } iio_uncore_sad_t;
30 : typedef u32 index_t;
31 :
32 : static const char *procfs_pci_path = "/proc/bus/pci";
33 :
34 : #define PCM_INTEL_PCI_VENDOR_ID 0x8086
35 : #define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4
36 : #define SNR_ICX_MESH2IIO_MMAP_DID 0x09A2
37 :
38 : static const u8 icx_sad_to_pmu_id_mapping[] = { 5, 0, 1, 2, 3, 4 };
39 :
40 : static const char *iio_bw_footer_message =
41 : "* this bundle currently only measures x8 and x16 PCIe devices on Port #0\n"
42 : "or Port #2. Please see the \"Intel® Xeon® Processor Scalable Memory\n"
43 : "Family Uncore Performance Monitoring Reference Manual(336274)\"\n"
44 : "Section 2.4 for more information.";
45 :
46 : static u32
47 0 : get_sad_ctrl_cfg (vlib_pci_addr_t *addr)
48 : {
49 0 : int fd = 0;
50 : u32 value;
51 0 : u8 *dev_node_name = format (0, "%s/%02x/%02x.%x", procfs_pci_path, addr->bus,
52 0 : addr->slot, addr->function);
53 :
54 0 : fd = open ((char *) dev_node_name, O_RDWR);
55 0 : if (fd < 0)
56 0 : return -1;
57 :
58 0 : if (pread (fd, &value, sizeof (u32), SNR_ICX_SAD_CONTROL_CFG_OFFSET) <
59 : sizeof (u32))
60 0 : value = -1;
61 :
62 0 : close (fd);
63 :
64 0 : return value;
65 : }
66 :
67 : static u64
68 0 : get_bus_to_sad_mappings (vlib_main_t *vm, index_t **ph, iio_uncore_sad_t **pp)
69 : {
70 0 : index_t *h = 0;
71 0 : iio_uncore_sad_t *p = 0, *e = 0;
72 0 : vlib_pci_addr_t *addr = 0, *addrs;
73 :
74 0 : addrs = vlib_pci_get_all_dev_addrs ();
75 :
76 0 : vec_foreach (addr, addrs)
77 : {
78 : vlib_pci_device_info_t *d;
79 0 : d = vlib_pci_get_device_info (vm, addr, 0);
80 :
81 0 : if (!d)
82 0 : continue;
83 :
84 0 : if (d->vendor_id == PCM_INTEL_PCI_VENDOR_ID &&
85 0 : d->device_id == SNR_ICX_MESH2IIO_MMAP_DID)
86 : {
87 :
88 0 : u32 sad_ctrl_cfg = get_sad_ctrl_cfg (addr);
89 0 : if (sad_ctrl_cfg == 0xFFFFFFFF)
90 : {
91 0 : vlib_pci_free_device_info (d);
92 0 : continue;
93 : }
94 :
95 0 : pool_get_zero (p, e);
96 :
97 0 : e->socket_id = (sad_ctrl_cfg & 0xf);
98 0 : e->sad_id = (sad_ctrl_cfg >> 4) & 0x7;
99 0 : e->iio_unit_id = icx_sad_to_pmu_id_mapping[e->sad_id];
100 :
101 0 : hash_set (h, addr->bus, e - p);
102 : }
103 :
104 0 : vlib_pci_free_device_info (d);
105 : }
106 :
107 0 : vec_free (addrs);
108 :
109 0 : *ph = h;
110 0 : *pp = p;
111 :
112 0 : return 0;
113 : }
114 :
115 : u8 *
116 0 : format_stack_socket (u8 *s, va_list *va)
117 : {
118 0 : iio_uncore_sad_t *e, *p = va_arg (*va, iio_uncore_sad_t *);
119 0 : index_t *h = va_arg (*va, index_t *);
120 0 : vlib_pci_addr_t root_bus, *addr = va_arg (*va, vlib_pci_addr_t *);
121 0 : clib_error_t *err = vlib_pci_get_device_root_bus (addr, &root_bus);
122 0 : if (err)
123 : {
124 0 : clib_error_free (err);
125 0 : return s;
126 : }
127 :
128 0 : uword *pu = hash_get (h, root_bus.bus);
129 0 : if (pu)
130 : {
131 0 : e = pool_elt_at_index (p, (index_t) pu[0]);
132 :
133 0 : s = format (s, "IIO%u/%u", e->socket_id, e->iio_unit_id);
134 : }
135 : else
136 : {
137 0 : s = format (s, "[ERR: hash lookup for bus '%u' failed]", root_bus.bus);
138 : }
139 0 : return s;
140 : }
141 :
142 : static clib_error_t *
143 0 : init_intel_uncore_iio_bw (vlib_main_t *vm, struct perfmon_bundle *b)
144 : {
145 0 : index_t *h = 0;
146 0 : iio_uncore_sad_t *p = 0;
147 0 : vlib_pci_addr_t *addr = 0, *addrs;
148 0 : u8 *s = 0;
149 :
150 0 : get_bus_to_sad_mappings (vm, &h, &p);
151 :
152 0 : s = format (0, "%-10s%-5s%-13s%-12s%-14s%-16s%s\n", "Stack", "Port",
153 : "Address", "VID:PID", "Link Speed", "Driver", "Product Name");
154 :
155 0 : addrs = vlib_pci_get_all_dev_addrs ();
156 :
157 0 : vec_foreach (addr, addrs)
158 : {
159 : vlib_pci_device_info_t *d;
160 0 : d = vlib_pci_get_device_info (vm, addr, 0);
161 :
162 0 : if (!d)
163 0 : continue;
164 :
165 0 : if (d->device_class != PCI_CLASS_NETWORK_ETHERNET)
166 0 : continue;
167 :
168 0 : s = format (
169 : s, "%-10U%-5U%-13U%04x:%04x %-14U%-16s%v\n", format_stack_socket, p,
170 : h, addr, format_vlib_pci_link_port, d, format_vlib_pci_addr, addr,
171 0 : d->vendor_id, d->device_id, format_vlib_pci_link_speed, d,
172 0 : d->driver_name ? (char *) d->driver_name : "", d->product_name);
173 :
174 0 : vlib_pci_free_device_info (d);
175 : }
176 :
177 0 : b->footer = (char *) format (s, "\n%s", iio_bw_footer_message);
178 :
179 0 : vec_free (addrs);
180 0 : pool_free (p);
181 0 : hash_free (h);
182 :
183 0 : return 0;
184 : }
185 :
186 : static u8 *
187 0 : format_intel_uncore_iio_bw (u8 *s, va_list *args)
188 : {
189 0 : perfmon_reading_t *r = va_arg (*args, perfmon_reading_t *);
190 0 : int col = va_arg (*args, int);
191 0 : f64 tr = r->time_running * 1e-9;
192 0 : f64 value = 0;
193 :
194 0 : switch (col)
195 : {
196 0 : case 0:
197 0 : s = format (s, "%9.2f", tr);
198 0 : break;
199 0 : default:
200 0 : if (r->time_running)
201 : {
202 0 : value = r->value[col - 1] * 4 / tr;
203 :
204 0 : if (value > 1.0e6)
205 0 : s = format (s, "%9.0fM", value * 1e-6);
206 0 : else if (value > 1.0e3)
207 0 : s = format (s, "%9.0fK", value * 1e-3);
208 : else
209 0 : s = format (s, "%9.0f ", value);
210 : }
211 :
212 0 : break;
213 : }
214 :
215 0 : return s;
216 : }
217 :
218 : /*
219 : * This bundle is currently only supported and tested on Intel Icelake.
220 : */
221 : static int
222 2236 : is_icelake ()
223 : {
224 2236 : return clib_cpu_supports_avx512_bitalg () && !clib_cpu_supports_movdir64b ();
225 : }
226 :
227 : static perfmon_cpu_supports_t iio_bw_cpu_supports[] = {
228 : { is_icelake, PERFMON_BUNDLE_TYPE_SYSTEM }
229 : };
230 :
231 559 : PERFMON_REGISTER_BUNDLE (intel_uncore_iio_bw_pci) = {
232 : .name = "iio-bandwidth-pci",
233 : .description = "pci iio memory reads and writes per iio stack *",
234 : .source = "intel-uncore",
235 : .events[0] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_OF_CPU_PART0_RD,
236 : .events[1] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART0_WR,
237 : .events[2] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_RD,
238 : .events[3] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_WR,
239 : .n_events = 4,
240 : .cpu_supports = iio_bw_cpu_supports,
241 : .n_cpu_supports = ARRAY_LEN (iio_bw_cpu_supports),
242 : .format_fn = format_intel_uncore_iio_bw,
243 : .init_fn = init_intel_uncore_iio_bw,
244 : .column_headers = PERFMON_STRINGS ("RunTime", "PCIe Rd/P0", "PCIe Wr/P0",
245 : "PCIe Rd/P2", "PCIe Wr/P2")
246 : };
247 :
248 559 : PERFMON_REGISTER_BUNDLE (intel_uncore_iio_bw_cpu) = {
249 : .name = "iio-bandwidth-cpu",
250 : .description = "cpu iio memory reads and writes per iio stack *",
251 : .source = "intel-uncore",
252 : .events[0] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART0_RD,
253 : .events[1] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART0_WR,
254 : .events[2] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_RD,
255 : .events[3] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_WR,
256 : .n_events = 4,
257 : .cpu_supports = iio_bw_cpu_supports,
258 : .n_cpu_supports = ARRAY_LEN (iio_bw_cpu_supports),
259 : .format_fn = format_intel_uncore_iio_bw,
260 : .init_fn = init_intel_uncore_iio_bw,
261 : .column_headers = PERFMON_STRINGS ("RunTime", "CPU Rd/P0", "CPU Wr/P0",
262 : "CPU Rd/P2", "CPU Wr/P2")
263 : };
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